As a preliminary matter, this invention concerns circuits that use voltages to represent binary logic values. A particular circuit may use varying voltage levels within its various sub-circuits to represent the two binary logic values. Accordingly, the words "high" and "low" in this specification generally refer to voltages corresponding to true and false binary logic values, respectively, within a given sub-circuit. Where binary signal lines are designated by a signal name, a "*" following the designation indicates that the signal line carries a voltage corresponding to the logical complement of the named signal. These conventions will be used in the following discussion of the invention.
To better understand the present invention and to more fully appreciate its contribution, two prior art circuits are shown in FIGS. 1 and 2 respectively and discussed below.
FIG. 1 shows a portion of a prior art CMOS integrated circuit, generally designated by the reference numeral 10, which includes a conventional output stage or output driver subcircuit 12. Integrated circuit 10 includes a supply voltage terminal 14, a ground terminal 16, and an output terminal 18. Supply voltage terminal 14 is connected to a source of positive voltage V.sub.cc which is external to the integrated circuit. Similarly, ground terminal 16 is connected to an external ground source V.sub.ss. An external circuit 20 is connected to output terminal 18. Output driver 12 is connected to output terminal 18 to transmit a digital signal to external circuit 20, through output terminal 18, to a high, low, or high impedance.
Output driver subcircuit 12 has a pull-up input line 22 that receives an input signal PULL-UP*. A pull-down input line 24 receives an input signal PULL-DOWN. These signals determine whether output driver 12 produces (1) a high, (2) a low, or (3) a high impedance at output terminal 18.
Such a conventional output driver 12 generally comprises a p-channel metal oxide semiconductor field effect transistor (MOSFET) pull-up device 26 and an n-channel MOSFET pull-down device 28. Pull-up transistor 26 has a source connected to a positive internal circuit source voltage, or V.sub.cc, and a drain connected to output terminal 18. Pull-down transistor 28 has a source connected to ground, or V.sub.ss, and a drain connected to output terminal 18. The gate of pull-up transistor 26 is connected to PULL-UP* through input line 22. The gate of pull-down transistor 28 is connected to PULL-DOWN through input line 24.
When PULL-UP* is active (low), p-channel pull-up transistor 26 conducts and drives output terminal 18 high. When PULL-DOWN is active (high), n-channel pull-down transistor 28 conducts and drives output terminal 18 low. If neither PULL-UP* or PULL-DOWN are active, neither pull-up transistor 26 or pull-down transistor 28 conducts. Accordingly, output driver 12 presents a high-impedance to output terminal 18 in this situation.
Such a conventional output driver subcircuit 12 is satisfactory for many applications. However, such a subcircuit has a significant limitation. Particularly, output terminals of certain integrated circuits are subjected to an external circuit voltage greater than V.sub.cc which allows significant output reverse leakage current back through output terminal 18 to the internal circuit. This is particularly undesirable for memory integrated circuits which are often connected to external circuits that are capable of generating excess voltages on output terminal 18. For instance, many dynamic and static random access memory integrated circuits specify no more than 10 .mu.A leakage current. This specification must be met even when output terminal 18 reaches a specified excess voltage, such as V.sub.cc +1.
Such a conventional output driver subcircuit 12 of FIG. 1 frequently permits a reverse current leakage in excess of 10 .mu.A. One reason for this is the bidirectional capability of MOSFETs. Current flows from output terminal 18 back through pull-up transistor 26 as the voltage at output terminal 18 exceeds V.sub.cc. If PULL-UP* is high, pull-up transistor 26 is normally reversed biased or off. However, pull-up transistor 26 becomes forward biased and allows reverse current leakage if the voltage at its drain exceeds the voltage at its gate by more than the transistor turn-on threshold voltage (generally less than 1.0 volt).
Reverse current leakage is also caused by forward biasing the p-n junction formed between the p-type drain and the n-type well of p-channel transistor 26. The n-wells of p-channel transistors are commonly biased to V.sub.cc. Accordingly, a voltage at output terminal 18 which exceeds V.sub.cc by more than the turn-on voltage of a silicon p-n junction (typically 0.7 volts) will forward bias the p-n junction between the drain and n-well of transistor 26, allowing current from output terminal 18 to V.sub.cc.
Thus, significant reverse leakage current through pull-up transistor 26 may occur whenever excess voltage from an external circuit is imposed upon output terminal 18, regardless of whether PULL-UP* is high or low.
FIG. 2 shows a second prior art output driver subcircuit within an integrated circuit 30. The second prior art output driver subcircuit is generally referenced by the numeral 32. Output driver 32 is similar to output driver 12 of FIG. 1 and includes an output terminal 34, a pull-up input line 36, a pull-down input line 38, and an n-channel MOSFET pull-down device 40. Output driver 32, however, has an n-channel MOSFET pull-up device 42, rather than the p-channel pull-up transistor 26 of FIG. 1. Pull-down input line 38 is connected to input signal PULL-DOWN. Pull-up input line 36 is connected to an active-high input signal PULL-UP rather than the active low signal of FIG. 1.
The source of pull-down transistor 40 is connected to V.sub.ss through a ground terminal 44. The drain of n-channel pull-up transistor 42 is connected to V.sub.cc through a supply voltage terminal 46. The drain of pull-down transistor 40 and the source of pull-up transistor 42 are connected in common to output terminal 34 which is, in turn, connected to an external circuit 47.
Output driver circuit 32 in operation is similar to output driver circuit 12 of FIG. 1, except for requiring an active-high signal at pull-up input line 36. An advantage of the second design is that the n-channel pull-up transistor 42 effectively prevents any reverse leakage current from output terminal 34. Specifically, when PULL-UP is low pull-up transistor 42 is off. Further, raising the voltage at output terminal 34 above V.sub.cc does not forward bias pull-up transistor 42. When PULL-UP is high, pull-up transistor 42 is on. However, an elevated voltage impressed on output terminal 34 reduces the gate to source voltage V.sub.gs of transistor 42. If the voltage or output terminal 34 exceeds V.sub.cc, V.sub.gs is less than the turn-on threshold voltage V.sub.T of transistor 42. Accordingly, pull-up transistor 42 turns off, preventing reverse current leakage, as the voltage at output terminal 34 approaches or exceeds V.sub.cc. Furthermore, by using an n-channel rather than a p-channel device, the drain to n-well p-n junction which allowed reverse current flow in output driver circuit 12 is eliminated.
However, while the second prior art output driver subcircuit 32 reduces or eliminates reverse current leakage, it creates other problems which are detrimental to the efficiency of many integrated circuits. The problems are created by the turn-on threshold voltage (V.sub.T) of pull-up transistor 42. V.sub.T ranges from approximately 0.5 volts to 1.0 volt in typical CMOS circuits which utilize standard MOS transistors. For pull-up transistor 42 to conduct, it must maintain a voltage equal to or greater than V.sub.T between its gate and its source, or between pull-up input line 36 and output terminal 34. Accordingly, since PULL-UP can be at a voltage no greater than V.sub.cc, the voltage at output terminal 34 cannot exceed V.sub.cc -V.sub.T. As the voltage at pull-up input line 36 approaches V.sub.cc -V.sub.T, therefore, pull-up transistor 42 begins to turn off. When the voltage at pull-up input line 36 reaches V.sub.cc -V.sub.T, pull-up transistor 42 is completely off.
Thus, the voltage to which output driver 32 can drive output terminal 34 is limited by the turn-on threshold voltage of pull-up transistor 42. Such a consequence is particularly undesirable when an integrated circuit is required to operate with a very low supply voltage. For instance, it is desirable in some cases to operate an integrated circuit at a circuit source voltage of as low as 3.0 volts. However, a high-logic output signal at output terminal 18 is specified to be no less than 2.4 volts. Achieving 2.4 volts at output terminal 18 with a circuit source voltage of 3.0 volts is either impossible or only marginally possible with standard n-channel transistors having turn-on threshold voltages of between 0.5 volts and 1.0 volts.
Even when operating at a more standard supply voltage such as 5.0 volts, use of an n-channel pull-up device 42 significantly slows output circuit operation. Output response time can be defined as the time required for an output terminal to reach an arbitrary voltage such as the minimum high-logic output voltage. FIG. 4 shows such output response times where the minimum high-logic output voltage is 2.4 volts. Line 48 shows the output voltage response with time of output driver 12, with a p-channel pull-up device. Line 49 shows the output voltage response with time of output driver 32, with an n-channel pull-up device. T.sub.1 indicates the relative output response time of output driver 12 and T.sub.2 indicates the relative output response time of output driver 32. Actual time responses depend on the impedances of external circuits 20 and 47, which are assumed to be equal. Only relative times are, therefore, shown. However, FIG. 4 reveals that the n-channel device of output driver 32 results in significantly slower output response time than does the p-channel pull-up device of output driver 12.
Consequently there remains a need for an output driver subcircuit which provides the comparatively quick response of a p-channel pull-up device while also providing the reverse output leakage prevention of an n-channel pull-up device. Furthermore, it is desirable for such a subcircuit to provide an output voltage at the output terminal which is nearly equal to V.sub.cc.